Image reading device

ABSTRACT

Delay circuit parts are disposed between a signal converting part and buffers. Since the capacities of delay elements provided respectively for the wiring of output wiring parts are different, time lag is generated respectively in the output timings of digital output signals outputted from the signal converting part relative to control clock signals. The output timings of the digital output signals shift so that the simultaneous switching of the digital output signals is prevented. Accordingly, EMI noise can be reduced without requiring the use of a special interface standard or the addition of shield members.

TECHNICAL FIELD

The present invention relates to an image reading apparatus.

BACKGROUND ART

In not only an image reading apparatus, but also an electronic computerand peripheral devices thereof (refer to the electronic computer and theperipheral devices thereof to as a “computer or the like”, hereinafter),the generation of noise due to the influence of an electromagnetic waveneeds to be reduced. The computer or the like is requested to performvarious kinds of processes at high speed. In order to perform theprocesses at high speed in the computer or the like, the frequency of aclock signal for adjusting the operating timing of elements or circuitsrespectively forming parts of the computer or the like. At present, thefrequency of the clock signal is widely set to several MHz to severalGHz.

However, it has been known that, when the frequency of the clock signalis raised, that is, when a high frequency is used for the clock signal,the generation of an electromagnetic shield noise, what is called an EMI(Electro Magnetic Interference) noise increases. The EMI noise has aproblem that the EMI noise is amplified when a switching operation (forinstance, 0 to 1 or 1 to 0) is performed at the same time synchronouslywith the clock signal, for instance, upon outputting the signal.

To reduce the EMI noise, a special interface standard such as an ECL oran SSTL has been hitherto used, cables of a transmission system or thelike have been coated with shield members, or EMI filters have beenprovided in all signal lines to reduce a noise level.

However, in the above-described case, the special interface standard isused or the shield members or the EMI filters need to be added.Consequently, a cost is increased.

Further, even when the special interface standard is used or the shieldmembers or the EMI filters are added as described above, theamplification of noise due to the simultaneous switching synchronouswith the clock signal is hardly reduced.

On the other hand, an image reading apparatus which has an image pick-upunit such as a CCD (Charge Coupled Device) to form digital image datafrom an analog electric signal outputted from the image pick-up unit andoutput the digital image data has been known. From the image pick-upunit of the image reading apparatus, the analog electric signal isoutputted as described above. The analog electric signal is outputted ata prescribed timing for each line. Therefore, the analog electric signaloutputted from the image pick-up unit needs to be specified to aprescribed output timing. Not only the image reading apparatus, but alsothe computer or the peripheral devices thereof use the clock signal of aprescribed frequency to specify the input and output timing of data or acalculating timing. The data is inputted and outputted or calculatedsynchronously with the clock signal.

In this image reading apparatus, a control signal synchronous with theclock signal is used to specify the output timing of the analog electricsignal from the image pick-up unit.

In a usual image reading apparatus, for instance, two control signalsare supplied to image pick-up unit to specify the output timing of ananalog electric signal in accord with a cross-point at which the twocontrol signals intersect. That is, the analog electric signal isoutputted from the image pick-up unit at the cross-point where the twocontrol signals intersect.

To allow the image pick-up unit to recognize the cross-point, voltage atthe cross-point needs to be located within a prescribed range.

However, the voltage at the cross-point is different for each type ofthe image pick-up unit, that is, every time the kind of the imagepick-up unit or a substrate changes. Each type of image pick-up unit hasspecific voltage characteristic of each image pick-up unit. Therefore,the voltage at the cross-point of the control signals needs to be set tothe specific voltage for each of the image pick-up unit. When thevoltage at the cross-point is not the specific voltage, the analogelectric signal is not outputted from the image pick-up unit.Accordingly, each image pick-up unit needs to be strictly adjusted sothat the voltage at the cross-point becomes the specific voltage.

Thus, a resistance element or a capacitor element or the like has beenhitherto disposed in a control signal circuit part for supplying acontrol signal to image pick-up unit. Thus, a resistance value or acapacity thereof has been adjusted to adjust the waveform of the controlsignal and voltage at a cross-point.

However, since the specific voltage is different for each image pick-upunit, the resistance value or the capacity of the resistance element orthe capacitor element needs to be adjusted for each image pick-up unit.Therefore, after the image pick-up unit is disposed on, for instance, asubstrate, an externally attached adjusting circuit including aresistance element or a capacitor element needs to be provided to adjustthe waveform of a control signal in accordance with the specific voltageof the image pick-up unit. As a result, the adjustment of the voltage atthe cross-point disadvantageously becomes complicated.

Accordingly, it is an object of the present invention to provide animage reading apparatus in which EMI noise is reduced and theamplification of noise due to a simultaneous switching operation isreduced without requiring the use of a special interface standard or theaddition of a shield member.

Further, it is another object of the present invention to provide animage reading apparatus in which voltage at a cross-point is easilyadjusted without requiring the adjustment of a waveform and anexternally attached circuit.

DISCLOSURE OF THE INVENTION

An image reading apparatus according to the first invention has outputtiming changing unit in an output side of an output signal generatingunit. The output timing changing unit changes the output timing of eachdigital output signal forming a plurality of digital output signalsoutputted from the output signal generating unit for each digital outputsignal. That is, the output timing of the digital output signaloutputted from the output signal generating unit is changed for each ofdigital output signals corresponding to the number of output bits.Therefore, the waveform of the digital output signal is different foreach digital output signal, so that the simultaneous switching can beprevented. Since the waveform of the digital output signal is differentfor each digital output signal, the current peaks of the outputtedsignals are dispersed to lower the peak of noise generated from cablesof a transmission system. As a result, EMI noise is reduced to improvean S/N ratio. Accordingly, the EMI noise can be reduced withoutrequiring the use of a special interface standard or the addition ofshield members and the amplification of noise due to the simultaneousswitching can be reduced.

Further, the output timing changing unit shifts the output timing inview of time for each digital output signal. Since a clock signal isessentially used to synchronize the operations of a computer such as theimage reading apparatus or the like, the digital output signalsspecified by the clock signal are also desirably outputted synchronouslywith the clock signal. However, as described above, the digital outputsignals are switched at the same time synchronously with the clocksignal to amplify the EMI noise. Thus, the output timing changing unitshifts the output timing so as not to avoid the synchronization of theclock signal with the digital output signal to prevent the simultaneousswitching of the digital output signals. For instance, in the clocksignal of a prescribed frequency, a reference clock signal is used sothat a phase can be adjusted during one cycle of the clock signal. Asdescribed above, the output timing of the digital output signal isshifted so that the simultaneous switching of the digital output signalscan be prevented and the amplification of the EMI noise can beprevented.

Further, delay circuit parts are respectively disposed in output wiringparts. The delay circuit parts respectively delay the output timings ofthe digital output signals in view of time. For instance, when theoutput signal generating unit is disposed on a substrate, the delaycircuit parts are merely disposed on the substrate. Accordingly, thedelay circuit parts are easily formed.

Further, the delay circuit parts are set so that an amount of delay ofthe output timing of the digital output signal is different for each ofthe delay circuit parts. Accordingly, the output timing of the digitaloutput signal is shifted for each digital output signal so that theamplification of the EMI noise due to the simultaneous switching can bereduced and noise generated due to the dispersion of current peaks canbe reduced.

Further, the output timing changing unit changes a frequency for eachdigital output signal. In other words, the output timing changing unitchanges a length of one cycle of the digital output signal, that is, awavelength. When the frequency of the digital output signal is changed,the output timing of the digital output signal is shifted for eachdigital output signal. As a result, the simultaneous switching of thedigital output signals can be prevented and the EMI noise can beprevented from being amplified.

Further, the output timing changing unit includes a plurality of delaycircuit parts respectively disposed in the output wiring parts and aselector for selecting an arbitrary delay circuit part from among theplural delay circuit parts. An amount of delay is set so as to bedifferent for each of the delay circuit parts. Then, when the selectorselects one delay circuit part, the amount of delay is different foreach output wiring part. Therefore, the output timing of the digitaloutput signal can be changed at random for each of the output wiringparts. Further, the output timing of the digital output signal ischanged at random for each output wiring part, so that not only theoutput timing, but also the frequency can be changed. Therefore, theamplification of the EMI noise due to the simultaneous switching and thenoise generated due to the dispersion of current peaks can be reduced.

An image reading apparatus according to the second invention includescross-point adjusting unit. The cross-point adjusting unit respectivelycontrols the amount of delay of a plurality of control signals in viewof time for each of the control signals to adjust voltage at across-point by adjusting the amount of delay of each control signal.Since the cross-point adjusting unit is provided, an externally attachedadjusting circuit does not need to be provided after image pick-up unitis provided. Accordingly, the amount of delay of the control signal canbe adjusted for each image pick-up unit by the cross-point adjustingunit. The capacity of an element of an externally attached circuit doesnot need to be adjusted, and accordingly, specific voltage and thevoltage at the cross-point are easily adjusted.

Further, the amount of delay of the plural control signals is adjustedfor each control signal. That is, the voltage at the cross-point isadjusted by adjusting the amount of delay. Therefore, the deteriorationof the control signal can be prevented and the incomplete operation ofthe image pick-up unit can be prevented.

Further, the image reading apparatus includes recording unit. Therecording unit can record the amount of delay of a plurality of controlsignals corresponding to the specific voltage in view of time.Accordingly, when the amount of delay of the control signal is recordedin the recording unit, for instance upon shipment, the voltage at thecross-point can be adjusted at any time on the basis of the recordedamount of delay.

Further, the cross-point adjusting unit includes a plurality of delaycircuit parts and a selector. The delay circuit parts respectivelychange an amount of delay in view of time for each control signal of theplural control signals supplied to the image pick-up unit. The pluraldelay circuit parts are provided to finely set the amount of delay foreach control signal. The selector selects a specific delay circuit partwith an amount of delay suitable for adjusting the voltage at the crosspoint from among the plural delay circuit parts. Thus, the amount ofdelay of the control signal can be finely controlled and the voltage atthe cross-point can be precisely controlled.

Further, the selector selects the specific delay circuit part on thebasis of the amount of delay recorded on the recording unit.Accordingly, the cross-point adjusting unit can always control thevoltage at the cross-point to a prescribed value.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic view showing a signal output part of an imagereading apparatus according to a first embodiment of the presentinvention.

FIG. 2 is a block diagram showing the image reading apparatus accordingto the first embodiment of the present invention.

FIG. 3 is a schematic view showing a timing chart of a case in whichoutput timing changing unit is not provided for comparison.

FIG. 4 is a schematic view showing a timing chart of the image readingapparatus according to the first embodiment of the present invention.

FIG. 5 is a schematic view showing a cross-point adjusting part of theimage reading apparatus according to the first embodiment of the presentinvention.

FIG. 6 is a schematic view showing a timing chart of a control signaloutputted from the cross-point adjusting part of the image readingapparatus according to the first embodiment of the present invention.

FIG. 7 is a schematic view showing a signal output part of an imagereading apparatus according to a second embodiment of the presentinvention.

FIG. 8 is a schematic view showing a timing chart of the image readingapparatus according to the second embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Now, a plurality of embodiments showing modes for carrying out thepresent invention will be described in detail by referring to thedrawings.

First Embodiment

An image reading apparatus according to a first embodiment is shown inFIG. 2. The image reading apparatus according to the first embodiment isa flat bed type image reading apparatus.

As shown in FIG. 2, the image reading apparatus 1 includes a carriage 20and a main control part 30 in a box shaped main body 10. A data holder11 is arranged on an upper part of the main body 10. A copy to be readis mounted on the part of the data holder 11 opposite to the carriageside. The carriage 20 disposed in the main body 10 can reciprocate in asub-scanning direction in parallel with the data holder 11 by a drivingdevice not shown in the drawing.

On the carriage 20, a light source 21, a converging lens 22, a linesensor 23 as image pick-up unit, an A/D converting part 24, a signaloutput part 40 as output signal generating unit and a carriage controlpart 26 are mounted.

The converging lens 22 converges light from data on the line sensor 23.As the line sensor 23, a charge storage type optical sensor such as aCCD in which a plurality of pixels are linearly arranged in a mainscanning direction perpendicular to the moving direction of the carriage20 is employed.

The light source 21 is provided perpendicularly to the moving directionof the carriage 20. A fluorescent lamp or the like is used. Lightapplied from the light source 21 is reflected on the surface of areflecting copy such as a sheet and incident on the line sensor 23.

The A/D converting part 24 converts an analog electric signal outputtedfrom the line sensor 23 to a digital electric signal. The signal outputpart 40 generates and outputs a plurality of digital output signalscorresponding to the number of bits from the digital electric signaloutputted from the A/D converting part 24. In the output side of thesignal output part 40, output timing changing unit 45 is provided.

The carriage control part 26 controls respective components of thecarriage 20 in accordance with an instruction from the main control part30. In the carriage control part 26, a clock generating part 261 isprovided as clock signal supply unit.

The main control part 30 includes a microcomputer 31, an imageprocessing ASIC (Application Specific IC) 32 and an interface 33. Themicrocomputer 31 includes a CPU (Central Processing Unit), a RAM (RandomAccess Memory) and a ROM (Read Only Memory) or the like which are notshown in the drawing to control the respective parts of the imagereading apparatus 1 via the image processing ASIC 32.

The image processing ASIC 32 includes a clock generating circuit 321,and a shading correction part, a gamma correction part and othercorrection parts that are not shown in the drawing. The clock generatingcircuit 321 supplies a basic clock signal to each part of the imagereading apparatus 1. The image processing ASIC 32 carries out variouskinds of processes to the digital output signal outputted from thesignal output part 40 of the carriage 20 to form digital image data.

The shading correction part carries out a shading correction to thedigital output signal outputted from the signal output part 40. Forexample, unevenness in the sensitivity for each pixel of the line sensor23 and unevenness in the quantity of light of the light source 21 in themain scanning direction are corrected by using data obtained by readinga white reference before a reading operation is started. The gammacorrection part carries out a gamma correction by a prescribed gammafunction to convert a shading corrected digital output signal to digitalimage data. Other correction part carries out various conversions suchas a color correction, an edge emphasis and enlargement/reduction ofarea, etc.

The digital image data prepared in the image processing ASIC 321 isoutputted to an image processor such as a personal computer connected toan external part from the interface 33.

In the clock generating circuit 321, the basic clock signal of a lowfrequency is generated. The generated basic clock signal is supplied tothe clock generating part 261 of the carriage control part 26. In theclock generating part 261, the basic clock signal of the low frequencygenerated in the clock generating circuit 321 is sequentially multipliedto generate a control clock signal. The control clock signal generatedin the clock generating part 261 is supplied to the line sensor 23, theA/D converting part 24 and the signal output part 40.

From the clock generating circuit 321 of the main control part 30, thebasic clock signal of the low frequency, for instance, about 6 Hz issupplied. The basic clock signal supplied to the carriage control part26 is multiplied by 16 in the clock generating part 261 and supplied tothe line sensor 23, the A/D converting part 24 and the signal outputpart 40 as the control clock signal of 96 MHz. The line sensor 23, theA/D converting part 24 and the signal output part 40 operatesynchronously with the supplied control clock signal.

An electric charge stored synchronously with the control clock signal isoutputted as an analog electric signal from the line sensor 23. In theA/D converting part 24, a digital electric signal is generated from theanalog electric signal. The generated digital electric signal isoutputted as a digital output signal synchronously with the controlclock signal from the signal output part 40.

The clock generating part 261 of the carriage control part 26sequentially multiplies the basic clock signal of the low frequencygenerated in the clock generating circuit 321 as clock signal generatingunit disposed in the main control part 30 to form an operating clocksignal of a high frequency. The operating clock signal generated in theclock generating part 261 is supplied to the line sensor 23, the A/Dconverting part 24, the signal output part 40 and a cross-pointadjusting part 50.

The cross-point adjusting part 50 generates a control signal from theoperating clock signal generated in the clock generating part 261 of thecarriage control part 26. The cross-point adjusting part 50 adjusts theamount of delay of the control signal and the cross-point of the controlsignal in accordance with an instruction from the main control part 30.

Now, the signal output part will be described in detail.

The signal output part 40 generates the digital output signalscorresponding to the number of output bits from the digital electricsignal outputted from the A/D converting part 24. In this embodiment, acase in which the number of output bits is 4 bits is described.

As shown in FIG. 1, the signal output part 40 has data wiring parts 41,a signal converting part 42 and an output wiring part 43. The datawiring parts 41 are electric wiring for connecting the A/D convertingpart 24 to the signal converting part 42. The signal converting part 42converts the digital electric signal inputted from the data wiring parts41 to the digital output signals corresponding to the number of outputbits. The output wiring part 43 is electric wiring for outputting thedigital output signals converted in the signal converting part 42.

The data wiring parts 41, the signal converting part 42 and the outputwiring part 43 are formed on a single substrate or a single chip toconstitute a signal output ASIC.

The output wiring part 43 has four wiring 430, 431, 432 and 433corresponding to the four bits as the number of output bits. Outputbuffers 44 are respectively provided in the four wiring 430 to 433. Theoutput buffers 44 improve the driving performance of the output signals.Between the signal converting part 42 and the output buffers 44, anoutput timing changing unit 45 for changing the output timing of theoutput signal is provided. The output timing changing unit 45 includesdelay circuit parts 451, 452 and 453 disposed respectively in the outputwiring part 43 between the signal converting part 42 and the outputbuffers 44. The delay circuit parts 451 to 453 are composed of delayelements, for instance, capacitors. The capacities of the delay elementsare different respectively for the delay circuit parts.

The control clock signal is supplied to the signal converting part 42from the clock generating part 261. From the signal converting part 42,the digital output signals corresponding to the number of output bitsare outputted synchronously with the control clock signal. For instance,when an output has 2 bits, a signal D0 and a signal D1 outputted fromthe wiring 430 and the wiring 431 of the output wiring part 43 are “1”,and a signal D2 and a signal D3 outputted from the wiring 432 and thewiring 433 are “0”. The digital output signals from the signalconverting part 42 are outputted to the image processing ASIC 32 of themain control part 30 via the output wiring part 43.

Now, an operation of the signal output part 40 will be described below.

As described above, the digital output signals are outputtedsynchronously with the control clock signal from the signal convertingpart 42. Therefore, for instance, when the output timing changing unit45 is not provided, the signals D0 to D3 outputted via the output wiringpart 43 are switched synchronously with the control clock signal asshown in FIG. 3. That is, as shown in FIG. 3, the signals simultaneouslychange from 0 to 1 or from 1 to 0 in an output timing tn (n is anarbitrary integer). Accordingly, as shown in a timing t0, all thesignals may be switched from “0” to “1” synchronously with the controlclock signal. When a plurality of signals are switched in the samemanner synchronously with the control clock signal as described above,EMI noise is amplified.

In this embodiment, the output timing changing unit 45 is providedbetween the signal converting part 42 and the output buffers 44. Thus,the output signals outputted from the signal converting part 42 havetime lag respectively generated in switching in the signals D0 to D3outputted from the wiring 430 to 433 depending on the capacities of thedelay elements of the delay circuit parts 451 to 453. As shown in FIG.1, when the delay element is not provided in the wiring 430 and thecapacities of the delay elements are increased in order in the wiring431, 432 and 433, signals D0 to D4 outputted from the signal convertingpart 42 have respectively time lag generated as shown in FIG. 4.

Therefore, even when the signals D0 to D4 are outputted synchronouslywith the clock signal, the switching from “0” to “1” or the switchingfrom “!” to “0” is not generated at the same time. As a result, theamplification of the EMI noise is reduced.

The signals D0 to D4 having the time lag generated by the output timingchanging unit 45 are inputted to the image processing ASIC 32 and thenthe time lag is adjusted synchronously with the basic clock signaloutputted from the clock generating circuit 321.

Now, the cross-point adjusting part 50 will be described in detail.

The cross-point adjusting part 50 is connected to the line sensor 23 asshown in FIG. 5. The cross-point adjusting part 50 includes controlsignal generating parts 51 for generating control signals, delay circuitparts 52, selectors 53 and control signal supply wiring parts 54. In thecontrol signal generating part 51, the control signal is generatedsynchronously with the operating clock signal supplied from the clockgenerating part 261. In this embodiment, two control signals aregenerated synchronously with the operating clock signal.

The delay circuit parts 52 are respectively provided in the line sensor23 side of the control signal generating parts 51 to change the amountsof delay of the control signals outputted from the control signalgenerating parts 51. Each delay circuit part 52 includes four delaycircuits 520, 521, 522 and 523 having delay elements respectively havingdifferent amounts of delay. The amount of delay means a time lag of thecontrol signals and its unit is “sec”. As the delay element, forinstance, a capacitor element or a resistance element is used. In thisembodiment, the amount of delay of the delay circuit 520 is set to 0nsec. The amount of delay of the delay circuit 521 is set to 1 nsec. Theamount of the delay circuit 522 is set to 3 nsec and the amount of delayof the delay circuit 523 is set to 8 nsec. These amounts of delay arecombined together so that the time lags of 0, 1, 2, 3, 5, 7 and 8 nsecscan be set to the control signals outputted from the two control signalgenerating parts 51. The selectors 53 are provided in the line sensor 23side of the delay circuit parts 52 to select specific delay circuitsfrom the delay circuits 520 to 523 forming the delay circuit parts 52 inaccordance with an instruction of the microcomputer 31 of the maincontrol part 30. When the selectors 53 select the specific delaycircuits, any of the above-described amounts of delay is set. Thecontrol signal supply wiring parts 54 supply the control signalsgenerated in the control signal generating parts 51 to the line sensor23.

Now, an operation of the cross-point adjusting part 50 will be describedbelow.

The output timing of the analog electric signal outputted from the linesensor 23 is controlled by the control signals. That is, as shown inFIG. 6, a cross-point P at which the control signals Φ1 and Φ2 outputtedfrom the two control signal generating parts 51 cross is specified asthe output timing of the analog electric signal from the line sensor 23.In other words, the analog electric signal is outputted from the linesensor 23 every time the two control signals Φ1 and Φ2 cross.

The line sensor 23 is set so that the line sensor outputs the analogelectric signal when voltage in the intersection of these controlsignals Φ1 and Φ2 is located within a prescribed range of, for instance,2.0 V to 3.0 V. The voltage of the cross-point P and the range of thevoltage are different respectively for various types of line sensors 23by setting in design and determined as specific cross-pointsrespectively for the line sensors 23. Accordingly, the amounts of delayof the control signals Φ1 and Φ2 need to be adjusted so that the voltageat the cross-point P is located within a range determined for each ofthe line sensors 23.

As shown in FIG. 6, when the specific voltage is set to 2.0 V to 3.0 V,the voltage of the cross-point P is not located within the range of thespecific voltage depending on the waveforms of the control signals Φ1and Φ2 as shown in FIG. 6(A). The deformation of the waveforms of thecontrol signals Φ1 and Φ2 is generated from various kinds of factorssuch as the capacities of pixels forming the line sensor 23 or thedifference of electric resistance for each wiring of the control signalsupply wiring parts 54 connected to the line sensor 23.

Thus, in this embodiment, as shown in FIG. 6(B), a time lag is generatedin the control signal Φ2, that is, the control signal Φ2 is delayed toadjust the voltage at the cross-point P to 2.0 V to 3.0 V as thespecific voltage.

The amounts of delay of the control signals Φ1 and Φ2 are set for eachtype of line sensors 23 and previously recorded in the ROM 342 of arecording part 34. Upon using the image reading apparatus 1, themicrocomputer 31 controls the selectors 53 on the basis of the amountsof delay recorded in the ROM 342 to select the delay circuits so as tohave prescribed amounts of delay. Therefore, in the two control signalsΦ1 and Φ2 outputted from the control signal generating parts 51, thevoltage in the cross-point P is adjusted to the specific voltage of theline sensor 23. The amounts of delay are controlled for each of outputtimings of the control signals.

For instance, in producing the image reading apparatus 1, when acarriage base 4 is previously produced, and then, the line sensor 23 ismounted on the carriage base 4, the amounts of delay of the controlsignals Φ1 and Φ2 are determined so as to correspond to the specificvoltage different for each of the line sensors 23 and the amounts ofdelay are stored in the ROM 342. Then, the microcomputer 31 controls theselectors 53 on the basis of the amounts of delay stored in the ROM 342to control the amounts of delay of the control signals Φ1 and Φ2.

Now, an operation of the above-described image reading apparatus 1 willbe described below.

A user mounts data desired to be read on the data holder 11 andinstructs the image reading apparatus 1 to start to read the data via adriver program for controlling the image reading apparatus 1 such as aTWAIN activated by a personal computer.

When the user instructs to start to read the data, the microcomputer 31turns on the light source 21. Then, the carriage 20 is moved in thesub-scanning direction at prescribed speed in accordance with theinstruction of the microcomputer 31. Light reflected on the data is madeincident on the line sensor 23. The incident light is converted into anelectric charge and the electric charge is stored. The stored electriccharge is transferred to a shift register (not shown) of the line sensor23 synchronously with the control clock signal and the analog electricsignal of one line is outputted from the line sensor 23. The analogelectric signal outputted from the line sensor 23 is outputted to theimage processing ASIC 32 via the A/D converting part 24 and the signaloutput part 40. The digital image data prepared in the image processingASIC 32 is outputted to the personal computer via the interface 33.

While the carriage 20 is moved in the sub-scanning direction atprescribed speed, the above-described processes are repeated to read thedata.

As described above, in the image reading apparatus 1 according to thefirst embodiment of the present invention, the digital output signalsoutputted from the signal converting part 42 of the signal output part40 are outputted with time lag by the delay circuit parts 451 to 453 ofthe output timing changing unit 45. Accordingly, the EMI noise due tothe simultaneous switching can be reduced.

Further, in the first embodiment, the delay circuit parts 451 to 453 aredisposed on a substrate on which the signal converting part 42 is formednear the output wiring part 43 of the signal converting part 42 or onthe same substrate as the chip or on the chip. Therefore, the delaycircuit parts 451 to 453 can be disposed simultaneously with theformation of the signal converting part 42, so that manufacturing stepsare not increased or a wiring structure is not complicated. Further,since the special interface or the shield members or the like forshielding the EMI noise are not necessary, the manufacture cost is notincreased.

Further, in the image reading apparatus 1 according to the firstembodiment of the present invention, a plurality delay circuits 520 to523 are provided in the cross-point adjusting part 50. Then, thespecific delay circuits are selected from these plural delay circuits520 to 523 so that the amounts of delay of the control signals Φ1 and Φ2can be accurately adjusted. Accordingly, voltage at the cross-point Pcan be easily adjusted within a range of the specific voltage. As aresult, even when the specific voltage of the line sensor 23 isdifferent for each image reading apparatus 1, an external circuit foradjusting the voltage at the cross-point P is not required and thevoltage at the cross-point P can be easily and accurately adjusted.

Further, the amounts of delay are recorded in the ROM 342 of therecording part 34. Thus, the amounts of delay are set, for instance,upon shipment, so that the amounts of delay of the control signals Φ1and Φ2 can be adjusted at any time during the use of the image readingapparatus 1.

Second Embodiment

A second embodiment of the present invention is shown in FIG. 7.Components substantially the same as those of the first embodiment aredesignated by the same reference numerals and the explanation thereofwill be omitted.

In the second embodiment, the structure of an output timing changingunit is different from that of the first embodiment. In the secondembodiment, the output timing changing unit includes a random enablesignal output part 61 and a select signal output part 62.

The random enable signal output part 61 generates a signal for changingthe output timing itself of a digital output signal outputted from asignal converting part 42 and outputs the signal to the signalconverting part 42.

In the signal converting part 42, a delay circuit part 63 is provided.The delay circuit part 63 is respectively connected to the signalconverting part 42. The delay circuit part 63 includes a plurality ofdelay circuits 630 to 633 respectively connected to the signalconverting part 42. The amounts of delay of circuits respectivelyforming the delay circuits 630 to 633 are different. For example, theamount of delay of the delay circuit 630 is 0. The amount of delay ofthe delay circuit 630 is respectively different from those of the delaycircuit 631, the delay circuit 632 and the delay circuit 633. In theoutput side of the delay circuits 630 to 633, selectors 634 aredisposed. The selectors 634 are connected to the select signal outputpart 62. The select signal output part 62 outputs a select signal toeach selector 634. Then, the selector 634 selects any of the delaycircuits 630 to 633 for each of output timings of the digital outputsignals outputted from the signal converting part 42 on the basis of theoutputted select signal. That is, since the delay circuit selected foreach output signal of the digital output signal is different dependingon the select signal outputted from the select signal output part 62,the output timings of the digital output signals outputted from thesignal converting part 42 are changed by a prescribed amount.

In a random enable signal or the select signal respectively outputtedfrom the random enable signal output part 61 and the select signaloutput part 62, a change point of the digital output signal is changedfor each clock in a specific area by using a clock signal of a cyclefaster than that of the clock signal generated in the clock generatingcircuit 321, for instance, a clock signal of 16 times as shown in FIG.8. That is, the change point of the digital output signal is changed byusing the control clock signal having a cycle faster than that of abasic clock signal in which data is sampled in the image processing ASIC32.

Now, an operation of the output timing changing unit according to thesecond embodiment will be described below.

As described above, the output timing of the digital output signaloutputted from the signal converting part 42 synchronously with thecontrol clock signal changes depending on the output timing itself ofthe signal converting part 42 and the amounts of delay of the delaycircuit part 63 connected to the signal converting part 42.Specifically, the output timing of the digital output signal outputtedfrom the signal converting part 42 changes in accordance with the randomenable signal outputted from the random enable signal output part 61.Further, since the selector 634 selects any of the delay circuits 630 to633 by the select signal outputted from the select signal output part62, the output timing of and the mount of delay of the digital outputsignal finely change for each clock signal. The random enable signal andthe select signal are outputted from the random enable signal outputpart 61 or the select signal output part 62 synchronously with thecontrol clock signal.

As described above, the output timing and the amount of delay of thedigital output signal are changed, so that the output timing of thedigital output signal changes at random as shown in FIG. 8. Usually, asshown in FIG. 8, digital output signals have been respectively outputtedat the same time from the signal converting parts 42 synchronously withthe basic clock and the control clock. As compared therewith, in thisembodiment, the output timing can be changed.

Frequency changed by the output timing changing unit is inputted to theimage processing ASIC 32, and then, the frequency is correctedsynchronously with the basic clock signal outputted from the clockgenerating circuit 321 and adjusted to a prescribed frequency.

In the second embodiment, the output timing of the digital output signalis changed at random to convert the output timing itself and thefrequency of the digital output signal. Therefore, the simultaneousswitching can be more effectively prevented and the amplification of theEMI noise can be reduced.

Further, in the second embodiment, the output timings of the digitaloutput signals that are outputted from the signal converting part 42 andthe amounts of delay of the outputted digital output signals arechanged. Therefore, even when the output timing of the digital outputsignal from one signal converting part accidentally overlaps the outputtiming from another signal converting part by the random enable signal,the amount of delay by the delay circuit is changed for each of theoutput timings of the digital output signals. Thus, the change points ofthe digital output signals do not coincide. Accordingly, the generationand amplification of the EMI due to the simultaneous switching of thedigital output signals can be more effectively prevented or reduced.

In the above plural embodiments, examples that the present invention isapplied to the flat bed type image reading apparatus are described.However, the present invention is not limited to the flat bed type.

1. An image reading apparatus comprising: an image pick-up unit whichconverts inputted light to an analog electric signal and outputs theanalog electric signal; an A/D converting part which converts the analogelectric signal outputted from the image pick-up unit to a digitalelectric signal; an output signal generating unit disposed in an outputside of the A/D converting part including a signal converting part,which generates a plurality of digital output signals corresponding tothe number of output bits on the basis of the digital electric signaland outputs the digital output signals; a plurality of output wiringparts provided in the output signal generating unit correspondingly tothe number of the output bits; a plurality of delay circuit partsrespectively disposed in the output wiring parts and delaying the outputtiming of the digital output signals; a selector for selecting one ofthe delay circuit parts; a clock signal supply unit which supplies clocksignals for specifying output timing of the digital output signals; andan output timing changing unit disposed in an output side of the outputsignal generating unit, which changes the output timing for each of thedigital output signals, wherein the output timing changing unitincludes: a random enable signal output part which changes, at random, achange point of the digital output signal outputted from the signalconverting part by using a control clock signal having a cycle fasterthan that of the clock signal supplied by the clock signal supply unit;and a select signal output part which outputs a select signal whichindicates, at random, the delay circuit part selected by the selector byusing a control clock signal having a cycle faster than that of theclock signal supplied by the clock signal supply unit.
 2. The imagereading apparatus according to claim 1, wherein the output timingchanging unit shifts the output timing in view of time for each of thedigital output signals.
 3. The image reading apparatus according toclaim 2, wherein the output timing changing unit includes delay circuitparts provided in the output wiring parts, respectively, each of whichdelays the output timing in view of time for each of the digital outputsignals.
 4. The image reading apparatus according to claim 3, whereinthe delay circuit part is set so that an amount of delay in time of eachof the digital output signals is different for each delay circuit part.5. The image reading apparatus according to claim 1, wherein the outputtiming changing unit changes a frequency for each of the digital outputsignals so as to shift the output timing for each of the digital outputsignals.
 6. An image reading apparatus comprising: an image pick-up unitwhich converts inputted light to an analog electric signal and outputsthe analog electric signal, a clock signal generating unit whichgenerates a clock signal for controlling an operating timing of theimage pick-up unit; a control signal generating unit which generates aplurality of control signals for controlling the output timing of theelectric signal synchronously with the clock signal; and a cross-pointadjusting unit which adjusts an amount of time delay for each of thecontrol signals and adjusts voltages at cross-points of the controlsignals to specific voltage characteristic of the image pick-up unit. 7.The image reading apparatus according to claim 6, further comprising arecording unit capable of recording the amount of time delay for each ofthe control signals.
 8. The image reading apparatus according to claim6, wherein the cross-point adjusting unit includes a plurality of delaycircuit parts for varying the amount of delay for each of the controlsignals and a selector for selecting a specific delay circuit part fromamong the delay circuit parts.
 9. The image reading apparatus accordingto claim 8, wherein the selector selects the specific delay circuit parton the basis of the amount of time delay recorded in the recording unit.